This invention relates generally to the fabrication of semiconductor devices and in particular to field effect transistors such as amorphous silicon thin film transistors (TFTs).
Thin film transistors fabricated from, among other materials, amorphous silicon, are commonly used to control arrays of solid state devices such as photodiodes, liquid crystals, or the like, which form the active parts of displays, facsimile devices, or imagers. Performance of such an array of active devices is typically enhanced by improving response (or switching) time of the TFTs, reducing switching transients and noise, reducing RC response time, and increasing the fill factor (i.e., increasing the portion of the total pixel area taken up by the active device in imager and display devices).
One important factor affecting performance is the contact resistance between conducting and semiconducting layers in the transistor. Contact resistance is one factor which determines the efficiency with which the TFT conducts a signal once the conductive channel in the semiconductor material has been established. Typically, TFTs include a doped semiconductor layer (that is, a layer of semiconductor material doped to exhibit a particular conductivity; typically for the devices discussed herein, this layer is doped to exhibit n+conductivity) disposed between the semiconductor layer and the source and drain electrodes to enhance the electrical contact between those components. It is desirable to reduce contact resistance at the interface between the amorphous silicon semiconductor material and the n+doped silicon. High resistance at this interface can result from degraded surface conditions, such as might be caused by impurities or physical degradation of the surface such as pitting or the like. Improved contact resistance at this interface, however, has numerous beneficial effects on TFT performance, such as making possible the construction of a small device with lower capacitance noise and transients associated with switching, and higher switching speeds.
It is thus desirable to fabricate TFTs through a process that produces a transistor having desirable electrical characteristics, such as low contact resistance between conductive and semiconductive layers. The fabrication process must also produce a device having mechanical characteristics, such as structural integrity and component arrangement, that enable it to exhibit the desired electrical characteristics when put to its intended use. For example, the device must not structurally deteriorate through loss of adhesion between the component layers of the device. Plasma-enhanced chemical vapor deposition (PECVD) is commonly used for depositing materials to form TFTs. The fabrication process necessarily involves deposition of multiple layers of material over a substrate and patterning portions of these layers to form the desired TFT island structures. The layers of materials should adhere well to one another during and after being exposed to these processing steps. It is desirable that any treatment to enhance structural stability be compatible with PECVD techniques, which require the device to be exposed to elevated temperatures, electric fields, and reduced pressure during the deposition processes.
It has been observed that treatment of portions of semiconductor devices with hydrogen can have advantageous effects. For example, Ihara and Nozaki reported in "Improvement of Hydrogenated Amorphous Silicon n-i-p Diode Performance by H.sub.2 Plasma Treatment for i/p Interface", Japanese Journal of Applied Physics, Vol. 29, pp. L2159-62 (December 1990), that exposing intrinsic silicon to a hydrogen plasma (during the fabrication process of a diode) prior to depositing a p+doped layer resulted in a diode having a slightly lower reverse current and a forward current of about one order of magnitude greater than the comparable currents in a similar device fabricated without the hydrogen plasma treatment. Ihara et al. postulate that the improved electrical performance results from fewer defects along the interface as a consequence of both the physical and chemical interactions of the hydrogen plasma with the intrinsic silicon in which impurities are removed from the surface and the surface is stabilized, making it difficult to oxidize.
It is thus an object of this invention to provide a method of fabricating a thin film transistor that consistently produces a TFT with low contact resistance between the amorphous silicon and n+doped silicon layer regardless of whether vacuum is broken between the deposition of these layers.
It is a still further object of this invention to provide a method of fabricating a TFT that exhibits good adhesion between layers of the device.